Integrated circuit ("IC") design and fabrication often involves a transfer of digital information from a circuit designer to fabrication facilities or foundries. The circuit designer must prepare a digital representation of circuit layout information in a format suitable for use by the foundry. Circuit designers also often use such digital circuit representations internally for automated schematic generation for verification and/or test of proposed circuit designs.
However, the current process by which circuit designers generate such digital representations from customer specifications is primarily manual in nature. The circuit designer must first manually design an appropriate circuit to meet a customer's functional and timing specifications. A designer must then manually lay out, or place and wire, the requisite components of a proposed circuit in an area and location of silicon which is commensurate with the customer's specifications. Computer-aided-design tools are currently available which facilitate this design process, however, the majority of the task is still very much a manual undertaking.
The customer specifications may also include fabrication of scaleable integrated circuit architectures. Field programmable gate arrays ("FPGAs") are an example of an architecture which may be considered scaleable or growable. At the device level, FPGAs are heterogeneous in nature, i.e., they are not comprised of a pure repetition of a single type of circuit. FPGAs rather comprise a multitude of different circuit types, which when viewed at higher levels of circuit type grouping, may be considered repetitive or scaleable. For example, a sector of FPGA logic cells may be defined as an M.times.N grouping of logic cells. A customer may require a family of ICs having 3.times.3, 5.times.5, 7.times.7, 9.times.9 . . . sectors. A customer may therefore specify that the same basic building blocks of an FPGA (e.g., a sector) be provided, but that multiple ICs be made available having a range of sizes measured in sectors. Multiple FPGA sizes may comprise an IC "family" which is often a useful way to market FPGAs to a user base.
However, from the standpoint of a circuit designer, an FPGA must be considered a collection of generally disparate circuit types (logic cells, interconnect, repeaters, etc.), because of the complexity and wiring requirements of each of these circuit types. To support fabrication of an FPGA family, multiple transfers of digital information to the foundry are required, one such transfer for each IC size. Using the known circuit design techniques discussed above, a primarily manual layout or place and wire procedure is necessary for each IC size. Thus, despite the apparent repetitive nature of FPGA circuits when viewed at higher levels, a designer must perform manual place and wire techniques for each IC size.
A method and system are thus required which automate the process by which a family of heterogeneous ICs can be designed and fabricated without unduly burdensome repetition of manual design and place and wire procedures.